1. Field of the Invention
The invention relates generally to a method of manufacturing semiconductor devices and, more particularly, to a method of manufacturing a flash memory device.
2. Discussion of Related Art
In general, the isolation film and the floating gate of a flash memory device are formed through the mask process. As the flash memory device is reduced, however, the overlay margin between a mask for the isolation film and a mask for the floating gate is reduced in size. The reduction in the overlay margin results in the generation of gate short failures between neighboring floating gates.
Furthermore, such a reduction in the overlay margin may generate cycling failures due to stress by the device driving without direct contact because the isolation film and the dielectric layer formed on the floating gate may be formed very closely.
In addition, in implementing NAND flash memory devices of 70 nm or less, the width of the floating gate formation region, which affects the cell current, also becomes reduced in size as the size of the cell pattern is reduced. It is therefore difficult to maintain an adequate level of cell current.
If the formation region width of the floating gate is increased within a limited area in a two-dimensional way in order to supplement these aspects, the width of a trench in which the isolation film will be formed is reduced in size much as the increased width. Consequently, since a gap-fill margin becomes small in the gap-fill process of the trench, there is a problem in that voids may occur in the isolation film.